This disclosure relates to integrated circuit devices, and more specifically, to a method and structure to create crack stop structures in semiconductor devices.
When a semiconductor wafer is diced into individual integrated circuit chips, cracks can form in the dicing region of the wafer. To prevent the crack from propagating from the dicing region into the active region of the chip, “crack stopper” or “crack stop” structures have been adopted by the industry to withstand the stresses resulting from the chip dicing operation during manufacturing. In the prior art, a crack stop structure comprised of a metal stack is built in a peripheral region surrounding active chip area, that is, the metal and dielectric interconnect levels which electrically connect the devices built deeper in the substrate.
With the adoption of low-k dielectrics, the effectiveness of the crack stop structures in stopping cracking proliferation has been reduced due to the brittleness of the low-k dielectrics as compared with the conventional dielectric materials. In addition to the problems caused by the low-k dielectrics, the stress level during the dicing operation is increasing in advanced chip designs due to a variety of factors such as increased chip size, organic laminate design, and the introduction of lead free solder metallurgies.
Thus, producing improved crack stop structures that can resist cracks driven by dicing induced stresses has become a critical issue for the industry. The present disclosure presents an advanced crack stop structure to alleviate this problem.